Magnetoresistive Random Access Memory (MRAM) is an emerging technology that may be competitive with prior integrated circuit memory technologies, such as floating gate technology. The MRAM technology may integrate silicon-based electronic components with magnetic tunnel junction technology. A significant element in MRAM is the magnetic tunnel junction (MTJ) where information may be stored. A MTJ stack has at least two magnetic layers separated by a non-magnetic barrier, where a pinned layer has a set magnetic property and a free layer has a programmable magnetic property for storing information. If the pinned layer and the free layer have parallel magnetic poles, the resistance through the MTJ stack is measurably less than if the pinned layer and the free layer have anti-parallel poles, so parallel magnetic poles may be read as a “0” and anti-parallel poles may be read as a “1.” The MTJ stack is typically incorporated into a memory cell, and many memory cells with MTJ stacks are incorporated into a memory bank.
The magnetic properties of the free layer may be changed when the memory cell is programmed, where the alignment of the free layer magnetic properties is changed relative to the fixed layer magnetic properties in the programming process. Programming changes the magnetic properties of the free layer and the fixed layer from anti-parallel to parallel, or from parallel to anti-parallel. The programming process typically includes applying a charge across the MTJ stack such that a programming current passes through the MTJ stack. Reductions in the current required to program the MTJ stack improve the overall efficiency of the integrated circuit. The free layer of the MTJ stack has a perpendicular magnetic anisotropy (PMA) value, and higher PMA values improve the operation of the MTJ stack. For example, higher PMA values can increase the difference in resistance of the MTJ stack between the parallel and anti-parallel states. Also, higher PMA values can decrease the required current to program the free layer. Thermal inertness is a measure of changes in the magnetic properties of the MTJ stack before and after exposure to a thermal event, such as higher temperatures associated with soldering reflow or annealing processes. Changes to the MTJ stack that increase the thermal inertness improve the robustness of the MTJ stack and the integrated circuit.
The stability of the magnetic pole in the free magnetic layer degrades as the temperature increases, and the free layer may become demagnetized if the temperature exceeds acceptable limits. A demagnetized free layer no longer retains stored information. The integrated circuit, and the components therein, are exposed to at least a reflow temperature for soldering, so the free layer needs to be capable of retaining its magnetic properties at the reflow temperature. Other integrated circuit processing steps may be desirable after formation of the MTJ, and MTJ stacks with higher thermal stability allow for processes with higher temperatures.
Accordingly, it is desirable to provide integrated circuits with magnetic tunnel junction stacks having higher thermal inertness, as compared to traditional magnetic tunnel junctions, and methods for producing the same. In addition, it is desirable to provide integrated circuits with magnetic tunnel junctions having higher thermal stability, and methods of producing the same. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.